1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for correcting a reference cell.
2. Description of the Related Art
A conventional semiconductor memory device will be described, while taking a flash memory as an example. The flash memory changes a threshold by injecting charge into a floating gate. By controlling this quantity of charge, the flash memory controls the threshold in a plurality of states and realizes multilevel storage. If data is stored in a flash memory which can control the threshold to turn into, for example, two states (one bit, respectively), data of 16 bits is stored in 16 flash cells, respectively. In case of a flash memory which can control the threshold to turn into four states (two bits, respectively), data of 16 bits can be stored in eight flash cells. To check which of, for example, four states the threshold turns into, a flash cell is compared with a flash memory that has a reference threshold.
However, the flash memory that has the reference threshold, i.e., a reference cell is accessed repeatedly. As shown in FIG. 2, for example, the reference cell is employed to be common to all flash cells. Due to this, the number of times of access to the reference cell is far greater than the number of times of access to a certain memory cell. In addition, as for a program reference cell used to check whether the threshold is equal to a specified threshold during program (write) or a read reference used to check a threshold corresponding to each storage state during read, once the threshold is set during a test, it is difficult to change the threshold later. Therefore, the conventional flash memory has disadvantages as follows. By repeatedly using the flash memory, the threshold of the reference cell lowers, which often makes it impossible to perform normal reading or programming. Further, in a multilevel memory cell, a threshold distribution range of which in a certain state is narrow, the deterioration of the reference cell is more serious.
To solve the disadvantages, the following method is proposed in U.S. Pat. No. 5,172,338. According to the U.S. Pat. No. 5,172,338, a reference cell is provided in each sector of a flash memory. The reference cells are simultaneously erased when the flash cell is performed block erasure and the reference cell in each block is reprogrammed using a master reference cell present independently of the other reference cells.
As multilevel rises, the range of a resistance corresponding to each storage state narrows. This requires high accuracy in the program reference cell and the read reference cell. However, by repeatedly performing a read operation (read), a program operation (program) and an erase operation (erase), the reference cell is disadvantageously deteriorated. As stated above, such a constitution that the reference cell is erased simultaneously with the block erasure and reprogrammed using the master reference cell is effective for a memory such as a flash memory that performs block erasure. However, if this constitution is adopted in a memory that erases data bit by bit, it is necessary to correct the reference cells whenever one bit is erased, which disadvantageously deteriorates efficiency.
It is, therefore, an object of the present invention to efficiently check a state of a reference cell, correct the reference cell, prevent a deterioration in the reference cell due to disturbance or the like, and highly accurately maintain a level of the reference cell so as to overcome the disadvantageous deterioration of the reference cell due to repetition of a read operation, a program operation, and an erase operation.
According to a first aspect of the present invention, there is provided a first characteristic constitution of a semiconductor memory device, i.e., a semiconductor memory device characterized by comprising: the plurality of memory cells each capable of storing and programming N-level data, where N is a natural number equal to or greater than 2; a reference cell storing a reference level used when reading a data level stored in the memory cells; a counter circuit counting number of times of reading of the reference cell; and check means for determining whether the reference level stored in the reference cell is within a preset range when the number of times of reading that is counted by the counter circuit reaches a specified value.
Namely, generally, a check processing for determining whether or not program is normally completed, erase is normally completed, or the like is performed whenever an arbitrary memory cell is accessed following a read operation, a program operation, and an erase operation for the arbitrary memory cell. Whenever the check processing is performed, a reference cell read operation is executed. The counter circuit counts the number of times of reading of the reference cell. When the number of times of reading counted reaches the specified value with which it is assumed that the reference level is not out of the variation allowable range, the check means determines whether the reference level stored in the reference cell is within the preset range. By doing so, the accuracy of the reference level is ensured without the need of checking it whenever the read operation, the program operation or the erase operation is performed. In this specification, a check processing for determining whether programming, erase or the like is normally completed by comparing the arbitrary memory cell with the reference cell or a check processing for determining whether the reference level stored in the reference cell is within the preset range, which check processing is performed whenever the memory cell is accessed following the read operation, the program operation, and the erase operation for the memory cell, is also referred to as xe2x80x9cverifyxe2x80x9d.
With the above-stated configuration, the counter circuit counts the number of times of reading of the reference cell in at least one of the read operation, the program operation, and the erase operation for the memory cell, whereby the check operation can be performed more efficiently. For example, if a stress causing a change of a threshold and applied to the reference cell differs among the read operation, the program operation, and the erase operation for the memory cell, it is preferable to count the number of times of reading following the operation in which the maximum stress is applied to the memory cell. By doing so, the check operation can be performed more efficiently.
According to a second aspect of the present invention, there is provided a second characteristic constitution of the semiconductor memory device, i.e., a semiconductor memory device characterized by comprising: the plurality of memory cells each capable of storing and programming N-level data, where N is a natural number equal to or greater than 2; a reference cell storing a reference level used when reading a data level stored in the memory cells; a timing generation circuit; and check means for determining whether the reference level stored in the reference cell is within a preset range, in synchronicity with a synchronous signal output from the timing generation circuit.
Namely, it is assumed that the occurrence of a malfunction caused by the deterioration of the reference cell correlates with stress accumulation time from an initial state until a stress at a predetermined level is accumulated. By checking the reference level at the predetermined timing before such a malfunction occurs, it is possible to ensure the accuracy of the reference level without the need of checking it whenever the read operation, the program operation or the erase operation is performed.
Besides the above constitution, if the semiconductor memory device is constituted so that if the check means determines that the reference level is out of the range, the correction means corrects the reference level to fall within the range, stable operation is always ensured.
If the correction of the reference level is made using the master reference level fixed to the master reference cell other than the reference cell, it is possible to ensure correcting the reference cell. This is because the master reference cell is accessed quite infrequently and, therefore, hardly deteriorated. It is preferable herein that the master reference cell consists of a fixed resistance element which does not cause deterioration by an electric stress.
It is preferable that the each of the memory cells and the reference cells consists of a nonvolatile variable resistance element, whose electric resistance is changed by an electric stress and remains on the changed electric resistance even after the electric stress is removed, and a select transistor. Preferably, the nonvolatile variable resistance element has a manganese-containing oxide of a perovskite structure formed between electrodes.
According to a third aspect of the present invention, there is provided a first characteristic constitution of a method for correcting a reference cell, i.e., a method for correcting a reference cell, the reference cell storing a reference level used when reading a data level stored in the plurality of memory cells each capable of storing and programming N-level data, where N is a natural number equal to or greater than 2, the method characterized by comprising the steps of: counting number of times of reading of the reference cell; determining whether the reference level stored in the reference cell is within a preset range when the number of times of reading that is counted reaches a specified value; and correcting the reference value to fall within the range if it is determined that the reference level is out of the range.
According to a fourth aspect of the present invention, there is provided a second characteristic constitution of the method for correcting a reference cell, i.e., a method for correcting a reference cell, the reference cell storing a reference level used when reading a data level stored in the plurality of memory cells each capable of storing and programming N-level data, where N is a natural number equal to or greater than 2, the method comprising the steps of determining whether the reference level stored in the reference cell is within a preset range, in synchronicity with a synchronous signal output from a timing generation circuit; and correcting the reference value to fall within the range if it is determined that the reference level is out of the range.